The escalating requirements for high density and performance associated with ultra large scale integration semiconductor wiring require integrated circuits of greater complexity with minimal feature sizes and spacings in the submicron range. High performance microprocessor applications require rapid speed of semiconductor circuitry. The control speed of semiconductor circuitry varies inversely with the resistance and capacitance of the interconnection pattern.
As integrated circuits become more complex and feature sizes and spacings become smaller, the integrated circuit speed becomes less dependent upon the transistor itself and more dependent upon the interconnection pattern. Thus, the interconnection pattern limits the speed of the integrated circuit.
Conventional integrated circuit technology basically comprises a semiconductor substrate, typically silicon, an insulating or dielectric layer on the silicon substrate, and a conductive layer comprising conductive patterns formed on the dielectric layer. Typically, a plurality of sequential dielectric and conductive layers are deposited in accordance with the design characteristics of a particular integrated circuit. The various conductive patterns of different conductive layers are electrically connected by vias or plugs, while the conductive patterns of the first conductive layer are electrically connected to active regions in the semiconductor substrate by contacts.
A conventional semiconductor device is schematically depicted in FIG. 1 and typically comprises a P-type semiconductor substrate 1 having active regions comprising source 2, 2' and drain 3, 3' regions isolated by a field oxide region 4. Also shown is N-type well 5, and gate electrodes 6, typically comprising polycrystalline silicon, spaced apart from the active regions by gate oxide 7. First dielectric layer 8 comprises a plurality of contacts 9 for electrically connecting the active regions 2, 2' and 3, 3' with conductive patterns of first conductive layer 10. Second dielectric layer 11 comprises a plurality of vias/plugs 12 for electrically connecting conductive patterns of the first conductive layer 10 with conductive patterns of the second conductive layer 13. Third dielectric layer 14 comprises a plurality of vias/plugs 15 for electrically connecting second conductive layer 13 to third conductive layer 16. A topside or protective dielectric layer 17 is then formed. The final conductive layer, such as third conductive layer 16, is typically joined to a bonding pad (not shown) for forming an external electrical connection and, hence, characterized as the wire bonding layer. The topside protective layer prevents contamination of the semiconductor device during assembling and provides resistance to moisture and chemical attack.
If the interconnection node is routed over a considerable distance, e.g., hundreds of microns or more, as in submicron technologies, the interconnection capacitance limits the circuit node capacitance loading and, hence, the circuit speed. As integration density increases and feature size decreases in accordance with submicron design rules, the rejection rate due to integrated circuit speed delays approaches and even exceeds 20%.
One way to increase the control speed of semiconductor circuitry is to reduce the resistance of a conductive pattern. Conventional metallization patterns are typically formed by depositing a layer of conductive material, notable aluminum or an alloy thereof, and etching, or by damascene techniques wherein trenches are formed in dielectric layers and filled with conductive material. The use of metals having a lower resistivity than aluminum, such as copper, engenders various problems which limit their utility. For example, copper readily diffuses through silicon dioxide, the typical dielectric material employed in the manufacture of semiconductor devices, and adversely affects the devices. Moreover, a low cost satisfactory method for joining a bonding pad to copper for external connection has yet to be developed. Furthermore, copper does not form a passivation film, as does aluminum. Hence, a separate passivation layer is required to protect copper from corrosion.
The dielectric constant of materials currently employed in the manufacture of semiconductor devices for dielectric interlayers spans from about 3.5 for dense silicon dioxide to over 8 for deposited silicon nitride and spin-on glass. Prior art attempts have been made to reduce the interconnect capacitance and, hence, increase the integrated circuit speed, by developing dielectric materials having a lower dielectric constant than that of silicon dioxide. New materials having low dielectric constants, such as low dielectric constant polymers, teflon, aerogels and porous polymers have been developed. There has been some use of certain polyimide materials for interlayer dielectrics which have a dielectric constant slightly below 3.0. However, polyimides in contact with aluminum, the typical metal employed for conductive patterns, create moisture/bias reliability problems.
There have been attempts to address the high capacitance interconnection problem by forming air bridges or air tunnels, such as disclosed in copending application Ser. No. 08/391,692 (our docket No. 1033-091 filed Feb. 21, 1995) now U.S. Pat. No. 5,670,828.These techniques however, require a considerable number of manipulative processing steps which are not only time consuming but expensive in terms of required equipment and materials. Moreover, the use of air bridges significantly reduces the structural integrity of the semiconductor device, since the conductive patterns are not provided with adequate underlying support.
Tomita et al., U.S. Pat. No. 5,034,799, disclose a semiconductor device based upon a gallium arsenide substrate, rather than silicon, wherein studs are employed and dielectric material is removed from under conductive patterns. The disclosed semiconductor device also exhibits inadequate structural integrity.
Thus, there exists a need for a semiconductor device, and method of manufacturing a semiconductor device, which exhibits a reduced interconnection capacitance and structural integrity in a simplified, cost effective manner.